1. Field of the Invention
This invention relates to, for example, a dynamic RAM (hereinafter, DRAM), and more particularly to a semiconductor memory device where the chip layout of memory cell arrays is improved.
2. Description of the Related Art
The most widely used DRAM families at present are those of .times.4 bits. Ordinary users now use fewer simple .times.1-bit DRAMs to increase the capacity of electronic equipment. Instead, they are requiring such DRAMs to serve as parts with added values such as the miniaturization of electronic equipment, lower-power dissipation, or higher performance. To meet these needs, DRAMs have been changing gradually from the 256K-bit age to those with more bits, and now the 4M-bit age is coming when DRAM products tend to contain more and more bits, centering around .times.8, .times.9, .times.16, and .times.18 bits.
FIGS. 22, 23, and 24 show chip layouts for constructing a .times.9-bit or .times.18-bit memory in conventional DRAMs or static RAMs (hereinafter, referred to as SRAMs). In FIG. 22, a parity cell array PCA is placed next to a row decoder of a memory 50. This parity cell array PCA corresponds to, for example, the 9th bit, 17th bit, and 18th bit of the memory cell array. In FIG. 23, a parity cell array PCA is located on the opposite side from a row decoder of a memory 60. FIG. 24 illustrates a chip layout where parity cell arrays PCA are provided at the left end of ordinary memory cell arrays (hereinafter, refereed to as NCAs).
With the tendency toward the increasing cell capacity, use of more bits, and more sophisticated functions, the memory chip size tends to increase. Equipment using memories, however, tends to be made more compact, so that it is difficult to make the package size, or the chip size, larger.
The layouts as shown in FIGS. 22 and 23 are best suited for products such as SRAMs whose cell array corresponds to the input/output terminal. In the case of products where a plurality of input/output terminals are provided in the cell array as found in DRAMs, a parity cell array PCA must be outputted from the selected cell array, resulting in the complicated circuit or pattern.
In the case of a chip layout as shown in FIG. 24, because the parity cell arrays PCA are away from the ordinary cell arrays NCA, the increased cell capacity and use of more bits require extra wiring and an additional control circuit. As a result, the chip size becomes larger, and the resulting chip not only cannot be put in a desired package but also is degraded in performance.